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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843001I-22
FEMTOCLOCKSTMCRYSTAL/LVCMOS-TO3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
FEATURES
* One 3.3V or 2.5V LVPECL output pair and one LVCMOS/LVTTL output * Selectable crystal oscillator interface or LVCMOS/LVTTL single-ended input * VCO range: 490MHz - 640MHz * Output frequency range: 490MHz - 640MHz * Supports the following applications: SONET, Ethernet, Fibre Channel, Serial ATA, and HDTV * RMS phase jitter @ 622.08MHz (12kHz - 20MHz): 0.80ps (typical) * Full 3.3V or 2.5V supply modes * -40C to 85C ambient operating temperature * Lead-Free package fully RoHS compliant
GENERAL DESCRIPTION
The ICS843001I-22 is a a highly versatile, low phase noise LVPECL/LVCMOS Synthesizer HiPerClockSTM which can generate low jitter reference clocks for a variety of communications applications and is a member of the HiPerClocksTM family of high performance clock solutions from ICS. The dual crystal interface allows the synthesizer to support up to two communications standards in a given application (i.e. 1GB Ethernet with a 25MHz crystal and 1Gb Fibre Channel using a 25.5625MHz cr ystal). The r ms phase jitter performance is typically less than 1ps, thus making the device acceptable for use in demanding applications such as OC48 SONET and 10Gb Ethernet. The ICS843001I-22 is packaged in a small 24-pin TSSOP package.
ICS
CONTROL INPUT FUNCTION TABLE
Control Input OE 0 1 FLOAT Outputs State Q0/nQ0, REF_CLK = High-Z Q0/nQ0 = High-Z, REF_CLK = Active Q0/nQ0 = Active, REF_CLK = High-Z
PIN ASSIGNMENT
VCCO_LVCMOS N0 N1 N2 VCCO_LVPECL Q0 nQ0 VEE VCCA VCC XTAL_OUT1 XTAL_IN1 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 REF_CLK VEE OE M2 M1 M0 MR SEL1 SEL0 TEST_CLK XTAL_IN0 XTAL_OUT0
BLOCK DIAGRAM
3
N2:N0 SEL0 Pulldown SEL1 Pulldown
ICS843001I-22
N 000 001 010 011 100 101 110 111 /1 /2 /3 /4 (default) /5 /6 /8 /10
XTAL_IN0
OSC
XTAL_OUT0
00
11
24-Lead TSSOP 4.40mm x 7.8mm x 0.92mm package body G Package Top View
Q0 nQO
XTAL_IN1
OSC
XTAL_OUT1 TEST_CLK Pulldown
01
Phase Detector
VCO
490MHz -640MHz
10 01 00
10
000 001 010 011 100 101
M /18 /22 /24 /25 /32 (default) /40
MR M2:M0
Pulldown
3
REF_CLK
OE
Pullup/Pulldown
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice. 843001AGI-22 www.icst.com/products/hiperclocks.html REV. A JUNE 17, 2005
1
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843001I-22
FEMTOCLOCKSTMCRYSTAL/LVCMOS-TO3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
Type Description Output supply pins. Pullup Output divider select pins. Default value = /4. Pulldown LVCMOS/LVTTL interface levels. See Table 3C. Differential output pair. LVPECL interface levels. Negative supply pin. Analog supply pin. Core supply pin. Parallel resonant cr ystal interface. XTAL_OUT1 is the output, XTAL_IN1 is the input. Parallel resonant cr ystal interface. XTAL_OUT0 is the output, XTAL_IN0 is the input. Pulldown LVCMOS/LVTTL clock input. Pulldown Input MUX select pins. LVCMOS/LVTTL interface levels. See Table 3D. Active HIGH Master Reset. When logic HIGH, the internal dividers are reset causing the true output Q0 to go low and the inver ted output nQ0 Pulldown to go high. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS/LVTTL interface levels. Pulldown Feedback divider select pins. Default value = /32. LVCMOS/LVTTL interface levels. See Table 3B. Pullup Pullup/ 3-State clock output enable, (High/Low/Float). LVCMOS/LVTTL interface Pulldown levels. See page 1, Control Input Function Table. Reference clock output. LVCMOS/LVTTL interface levels.
TABLE 1. PIN DESCRIPTIONS
Number 1, 5 2, 3 4 6, 7 8, 23 9 10 11 12 13 14 15 16, 17 18 19, 20 21 22 24 Name VCCO_LVCMOS, VCCO_LVPECL N0, N1 N2 Q0, nQ0 VEE VCCA VCC XTAL_OUT1, XTAL_IN1 XTAL_OUT0, XTAL_IN0 TEST_CLK SEL0, SEL1 MR M0, M1 M2 OE REF_CLK
Power Input Input Ouput Power Power Power Input Input Input Input Input Input Input Input Output
NOTE: Pulldown and Pullup refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLDOWN RPULLUP Rout Parameter Input Capacitance Input Pulldown Resistor Input Pullup Resistor Output Impedance REF_CLK Test Conditions Minimum Typical 4 51 51 15 Maximum Units pF k k
843001AGI-22
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REV. A MAY 4, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843001I-22
FEMTOCLOCKSTMCRYSTAL/LVCMOS-TO3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
Output Frequency (MHz) 74.25 70 74.25 200 74.1758245 155.52 77.76 622.08 311.04 156.25 250 125 62.5 1 00 150 75 106.25 212.5 159.375 187.5 HDTV SONET SONET SONET SONET 10 GigE Ethernet 1 GigE 1 GigE PCI Express SATA SATA Fibre Channel 1 4 Gig Fibre Channel 10 Gig Fibre Channel 12 Gig Ethernet HDTV
TABLE 3A. COMMON CONFIGURATIONS TABLE
Input Reference Clock (MHz) 27 22.4 24.75 25 14.8351649 19.44 19.44 19.44 19.44 19.53125 20 25 25 25 25 25 26.5625 26.5625 26.5625 31.25 M Divider Value 22 25 24 24 40 32 32 32 32 32 25 25 25 24 24 24 24 24 24 18 N Divider Value 8 8 8 3 8 4 8 1 2 4 2 5 10 6 4 8 6 3 4 3 VCO (MHz) 594 560 594 600 593.4066 622.08 622.08 622.08 622.08 625 500 625 625 600 600 600 637.5 637.5 637.5 562.5 Application HDTV
TABLE 3B. PROGRAMMABLE M OUTPUT DIVIDER FUNCTION TABLE
Inputs M2 0 0 0 0 1 1 M1 0 0 1 1 0 0 M0 0 1 0 1 0 1 M Divider Value 18 22 24 25 32 40 Input Frequency (MHz) Minimum 27.22 22.27 20.41 19.6 15.31 12.25 Maximum 35.56 29.09 26.67 25.6 20 16
TABLE 3C. PROGRAMMABLE N OUTPUT DIVIDER FUNCTION TABLE
Inputs N2 0 0 0 0 1 1 1 1 N1 0 0 1 1 0 0 1 1 N0 0 1 0 1 0 1 0 1 N Divide Value 1 2 3 4 (default) 5 6 8 10
TABLE 3D. BYPASS MODE FUNCTION TABLE
Inputs SEL1 0 0 1 1
843001AGI-22
SEL0 0 1 0 1
Reference Input XTAL0 XTAL1 TEST_CLK TEST_CLK
PLL Mode Active Active Active Bypass
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3
REV. A JUNE 17, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843001I-22
FEMTOCLOCKSTMCRYSTAL/LVCMOS-TO3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
4.6V -0.5V to VCC + 0.5V 50mA 100mA -0.5V to VCCO + 0.5V 70C/W (0 lfpm) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC Inputs, VI Outputs, IO (LVPECL) Continuous Current Surge Current Outputs, VO (LVCMOS) Package Thermal Impedance, JA Storage Temperature, TSTG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = VCCO_LVCMOS, VCCO_LVPECL= 3.3V10%, TA = -40C TO 85C
Symbol VCC VCCA VCCO_LVPECL, _LVCMOS IEE ICCO_LVPECL, _LVCMOS Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Output Supply Current Test Conditions Minimum 2.97 2.97 2.97 Typical 3. 3 3. 3 3.3 115 5 Maximum 3.63 3.63 3.63 Units V V V mA mA
TABLE 4B. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = VCCO_LVCMOS, VCCO_LVPECL = 2.5V5%, TA = -40C TO 85C
Symbol VCC VCCA VCCO_PECL, _LVCMOS IEE ICCO_PECL, _LVCMOS Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Output Supply Current Test Conditions Minimum 2.375 2.375 2.375 Typical 2.5 2.5 2.5 110 5 Maximum 2.625 2.625 2.625 Units V V V mA mA
843001AGI-22
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REV. A MAY 4, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843001I-22
FEMTOCLOCKSTMCRYSTAL/LVCMOS-TO3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
Test Conditions VCC = 3.3V 10% VCC = 2.5V 5% VCC = 3.3V 10% VCC = 2.5V 5% VCC = VIN = 3.63V or 2.625V VCC = VIN = 3.63V or 2.625V VCC = 3.63V or 2.625V, VIN = 0V VCC = 3.63V or 2.625V, VIN = 0V VCCO_LVCMOS = 3.63V Minimum Typical 2 1.7 -0.3 -0.3 Maximum VCC + 0.3 VCC + 0.3 0.8 0.7 150 5 -5 -150 2.6 Units V V V V A A A A V V 0.5 V
TABLE 4C. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = VCCA = VCCO_LVCMOS = 3.3V10% OR 2.5V5%, TA = -40C TO 85C
Symbol VIH VIL Parameter Input High Voltage Input Low Voltage TEST_CLK, SEL0, SEL1, MR, M0, M1, N2, OE M2, N0, N1 TEST_CLK, SEL0, SEL1, MR, M0, M1, N2, OE M2, N0, N1 VOH Output High Voltage; NOTE 1
IIH
Input High Current
IIL
Input Low Current
VCCO_LVCMOS = 2.625V 1.8 VCCO_LVCMOS = 3.63V or VOL Output Low Voltage: Note 1 2.625V NOTE 1: Outputs terminated with 50 to VCCO _LVCMOS/2. See Parameter Measurement Information Section, "Output Load Test Circuit Diagram".
TABLE 4D. LVPECL DC CHARACTERISTICS, VCC = VCCA = VCCO_LVPECL = 3.3V10% OR 2.5V5%, TA = -40C TO 85C
Symbol VOH VOL VSWING Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Peak-to-Peak Output Voltage Swing Test Conditions Minimum VCCO - 1.4 VCCO - 2.0 0.6 Typical Maximum VCCO - 0.9 VCCO - 1.7 1. 0 Units V V V
NOTE 1: Outputs terminated with 50 to VCCO_PECL - 2V.
TABLE 5. CRYSTAL CHARACTERISTICS
Parameter Mode of Oscillation Frequency Equivalent Series Resistance (ESR) Shunt Capacitance Drive Level NOTE: Characterized using an 18pF parallel resonant crystal. 12 Test Conditions Minimum Typical Maximum 40 50 7 1 Units MHz MHz pF mW Fundamental
843001AGI-22
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REV. A JUNE 17, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843001I-22
FEMTOCLOCKSTMCRYSTAL/LVCMOS-TO3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
Test Conditions Minimum 49 622.08MHz (12kHz - 20MHz) 490 20% to 80% 450 50 0.80 640 Typical Maximum 640 Units MH z ps MH z ps %
TABLE 6A. AC CHARACTERISTICS, VCC = VCCA = VCCO_LVCMOS, VCCO_LVPECL = 3.3V10%, TA = -40C TO 85C
Symbol fOUT Parameter Output Frequency RMS Phase Jitter, (Random); NOTE 1, 2 PLL VCO Lock Range Output Rise/Fall Time
tjit(O)
fVCO t R / tF
odc Output Duty Cycle NOTE 1: Phase jitter using a crystal interface. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
TABLE 6B. AC CHARACTERISTICS, VCC = VCCA = VCCO_LVCMOS, VCCO_LVPECL= 2.5V5%, TA = -40C TO 85C
Symbol fOUT Parameter Output Frequency RMS Phase Jitter, (Random); NOTE 1, 2 PLL VCO Lock Range Output Rise/Fall Time Test Conditions Minimum 49 622.08MHz (12kHz - 20MHz) 490 20% to 80% 450 50 0.80 640 Typical Maximum 640 Units MH z ps MH z ps %
tjit(O)
fVCO t R / tF
odc Output Duty Cycle NOTE 1: Phase jitter using a crystal interface. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
843001AGI-22
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6
REV. A MAY 4, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843001I-22
FEMTOCLOCKSTMCRYSTAL/LVCMOS-TO3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
TYPICAL PHASE NOISE AT 622.08MHZ
0 -10 -20 -30 -40 -50
OC-12 Filter 622.08MHz
RMS Phase Jitter (Random) 12kHz to 20MHz = 0.80ps (typical)
NOISE POWER dBc Hz
-60 -70 -80 -90 -100 -110
Raw Phase Noise Data
-130 -140 -150 -160 -170 -180 -190 100 1k
Phase Noise Result by adding Sonet OC-12 Filter to raw data
10k
-120
100k
1M
10M
100M
OFFSET FREQUENCY (HZ)
843001AGI-22
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7
REV. A JUNE 17, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843001I-22
FEMTOCLOCKSTMCRYSTAL/LVCMOS-TO3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
PARAMETER MEASUREMENT INFORMATION
2V
1.6510%
VCC, VCCA, VCCO_LVPECL
Qx
SCOPE
VCC, VCCA, VCCO_LVCMOS
Qx
SCOPE
LVPECL
VEE
nQx
LVCMOS
VEE
-1.3V0.33V
-1.65V10%
3.3V LVPECL OUTPUT LOAD AC TEST CIRCUIT
2V
3.3V LVCMOS OUTPUT LOAD AC TEST CIRCUIT
1.25V5%
VCC, VCCA, VCCO_LVPECL
Qx
SCOPE
VCC, VCCA, VCCO_LVCMOS
Qx
SCOPE
LVPECL
nQx
LVCMOS
VEE
VEE
-0.5V 0.125V
-1.25V5%
2.5V LVPECL OUTPUT LOAD AC TEST CIRCUIT
2.5V LVCMOS OUTPUT LOAD AC TEST CIRCUIT
Phase Noise Plot
Noise Power
V
DDO_LVCMOS
REF_CLK
2
t PW
Phase Noise Mask
t
PERIOD
odc =
f1 Offset Frequency f2
t PW t PERIOD
x 100%
RMS Jitter = Area Under the Masked Phase Noise Plot
RMS PHASE JITTER
843001AGI-22
LVCMOS OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
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8
REV. A MAY 4, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843001I-22
FEMTOCLOCKSTMCRYSTAL/LVCMOS-TO3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
nQ0 Q0
t PW
t
PERIOD
80% 20% tR
80% 20% tF
Clock Outputs
x 100%
odc =
t PW t PERIOD
LVPECL OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
LVCMOS OUTPUT RISE/FALL TIME
80% Clock Outputs
80% VSW I N G
20% tR tF
20%
LVPECL OUTPUT RISE/FALL TIME
843001AGI-22
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9
REV. A JUNE 17, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843001I-22
FEMTOCLOCKSTMCRYSTAL/LVCMOS-TO3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS843001I-22 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VCC, VCCA, and VCCO_x should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 10 resistor along with a 10F and a .01F bypass capacitor should be connected to each VCCA.
3.3V or 2.5V VCC .01F V CCA .01F 10F 10
FIGURE 1. POWER SUPPLY FILTERING
TERMINATION
FOR
3.3V LVPECL OUTPUT
designed to drive 50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 2A and 2B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations.
The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are
Zo = 50
125
3.3V 125
FOUT
FIN
Zo = 50
Zo = 50
FOUT FIN
50 1 Z ((VOH + VOL) / (VCC - 2)) - 2 o
50 VCC - 2V RTT
84 84 Zo = 50
RTT =
FIGURE 2A. LVPECL OUTPUT TERMINATION
FIGURE 2B. LVPECL OUTPUT TERMINATION
843001AGI-22
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REV. A MAY 4, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843001I-22
FEMTOCLOCKSTMCRYSTAL/LVCMOS-TO3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
ground level. The R3 in Figure 3B can be eliminated and the termination is shown in Figure 3C.
TERMINATION
FOR
2.5V LVPECL OUTPUT
Figure 3A and Figure 3B show examples of termination for 2.5V LVPECL driver. These terminations are equivalent to terminating 50 to VCC - 2V. For VCCO = 2.5V, the VCCO - 2V is very close to
2.5V 2.5V VCCO=2.5V R1 250 Zo = 50 Ohm + Zo = 50 Ohm 2,5V LVPECL Driv er R2 62.5 R4 62.5 R3 250
2.5V VCCO=2.5V Zo = 50 Ohm + Zo = 50 Ohm 2,5V LVPECL Driv er R1 50 R2 50
R3 18
FIGURE 3A. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
FIGURE 3B. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
2.5V VCCO=2.5V Zo = 50 Ohm + Zo = 50 Ohm 2,5V LVPECL Driv er R1 50 R2 50
FIGURE 3C. 2.5V LVPECL TERMINATION EXAMPLE
CRYSTAL INPUT INTERFACE
The ICS843001I-22 has been characterized with 18pF parallel resonant crystals. The capacitor values shown in Figure 4 below were determined using a 26.5625MHz 18pF parallel resonant crystal and were chosen to minimize the ppm error.
XTAL_IN C1 22p X1 18pF Parallel Cry stal XTAL_OUT C2 22p
ICS843001I-22 ICS84332
Figure 4. CRYSTAL INPUt INTERFACE
843001AGI-22
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11
REV. A JUNE 17, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843001I-22
FEMTOCLOCKSTMCRYSTAL/LVCMOS-TO3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER RELIABILITY INFORMATION
TABLE 7. JAVS. AIR FLOW TABLE
FOR
24 LEAD TSSOP
JA by Velocity (Meters per Second)
0
Multi-Layer PCB, JEDEC Standard Test Boards 70C/W
1
65C/W
2.5
62C/W
TRANSISTOR COUNT
The transistor count for ICS843001I-22 is: 3881
843001AGI-22
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12
REV. A MAY 4, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843001I-22
FEMTOCLOCKSTMCRYSTAL/LVCMOS-TO3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
24 LEAD TSSOP
PACKAGE OUTLINE - G SUFFIX
FOR
TABLE 8. PACKAGE DIMENSIONS
SYMBOL N A A1 A2 b c D E E1 e L aaa 0.45 0 -4.30 0.65 BASIC 0.75 8 0.10 -0.05 0.80 0.19 0.09 7.70 6.40 BASIC 4.50 Millimeters Minimum 24 1.20 0.15 1.05 0.30 0.20 7.90 Maximum
Reference Document: JEDEC Publication 95, MO-153
843001AGI-22
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13
REV. A JUNE 17, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843001I-22
FEMTOCLOCKSTMCRYSTAL/LVCMOS-TO3.3V, 2.5V LVPECL FREQUENCY SYNTHESIZER
Marking Package 24 Lead TSSOP 24 Lead TSSOP 24 Lead "Lead-Free" TSSOP 24 Lead "Lead-Free" TSSOP Shipping Packaging tube 2500 tape & reel tube 2500 tape & reel Temperature -40C to 85C -40C to 85C -40C to 85C -40C to 85C
TABLE 9. ORDERING INFORMATION
Part/Order Number ICS843001AGI-22 ICS843001AGI-22T ICS843001AGI-22LF ICS843001AGI-22LFT ICS843001AI22 ICS843001AI22 ICS43001AI22L ICS43001AI22L
NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant.
The aforementioned trademarks, HiPerClockSTM and FemtoClocksTM are a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 843001AGI-22
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REV. A MAY 4, 2005

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